The present invention relates to the field of binary adder circuits and, more particularly, to circuitry for modifying truncated result data under out-of-range conditions.
Various binary adders are known. Examples includes carry-save adders, carry lookahead adders, etc. A full adder receives two binary operands and sums them to provide a single binary result. Full adder circuitry includes a predetermined number of bit positions. Each bit position or adder "cell" receives a corresponding bit of each operand, and provides a corresponding sum bit. The sum bits from all cells in the adder, taken together in an ordered series, form the result.
Each full adder cell also has a carry input terminal and a carry output terminal for interconnecting the cell to other cells in the adder. The result may also include a most significant bit (msb) taken from a carry output of the most significant cell.
The range of an adder circuit is the range of numbers that can be represented as the result. This range depends upon the number of bits or cells in the adder, and upon the number representation convention used. For example, integers may be represented as signed or unsigned. Signed integers may be represented using complement codes such as two's complement representation. Using a two's complement signed represented in the most significant or "sign bit" position (msb) as 1 for a negative number and 0 for a positive number. The result range using, for example, 16 bits thus is +2.sup.15 -1 (represented as 011 . . . 111) to -2.sup.15 (represented as all ones).
An overflow condition exists when the result of summing the two operands exceeds the result range. The term "overflow" is often used generically to include both positive and negative results outside the available range. I will use the terms overflow and underflow to distinguish these two cases, respectively. For many applications, overflow and underflow conditions must be detected because the adder result may be erroneous.
In the two's complement system, the result will be erroneous when both summands are positive and there is a carry into the sign bit. Indeed, in this overflow condition, the magnitude of the error is very substantial because the apparent result is negative (the sign bit is a one), when in fact the correct result is a positive number that exceeds the adder range. Just the opposite occurs in an underflow condition. The sum of two negative summands appears to be a positive number, unless there is a carry into the sign bit. See S. Waser and M. Flynn, INTRODUCTION TO ARITHMETIC FOR DIGITAL SYSTEMS DESIGNERS pp. 12-13 (Holt, Rinehart and Winston 1982). Truncation errors of the type described are unacceptable in many designs, for example, where the adder result is input to a DAC to form an analog signal.
While adder results cannot be represented correctly when they exceed the range of the adder, the magnitude of the error can be minimized by forcing the result to a maximum representable value in response to an overflow condition and, similarly, forcing the result to a minimum representable value in response to an underflow condition. For example, U.S. Pat. No. 4,511,922 (the '922 patent) is directed to a digital television system with truncation error correction. The '922 patent, FIG. 3, shows a synchronous circuit in which adder (46) result bits are input to a latch (48) consisting essentially of D-type flip-flop circuits. The adder includes an extra bit position .SIGMA..sub.R which sums replicated sign bits A.sub.R and B.sub.R.
An overflow condition drives preset inputs to the flip-flops (75) to force all the flip-flop outputs HIGH on the next clock signal. Similarly, an underflow condition drives reset inputs to the flip-flops (76) to force all the flip-flop outputs LOW on the next clock signal. The '922 circuit thus delays the adder results under all conditions until a next clock cycle. The '922 circuit also employs a large number of devices and therefore increases circuit size. Delay time through the flip-flops adds to the clock signal delay, all of which results in relatively slow operation.